In the development of semiconductor packaging technology it has been the experience that succeeding generations of products of similar function, but having far greater density, are used to replace earlier production versions. One of the packaging constraints placed on the superseding product is a desire that a plurality of substantially identical semiconductor devices be mounted on a common carrier, be it a module or an integrated circuit card. Because of the increased capacitive loading encountered by the multiplication of circuit devices, input signal drivers originally designed for a single integrated circuit are required to drive several circuit devices.
In fabricating semiconductor memory devices it is common to package a number of memory chips or modules on a single assembly or subassembly identified as a single in-line package (SIP) or a single in-line memory module (SIMM) in which all of the memory components share a plurality of signal lines. The total capacitive load to be driven can approach several nano-farads for a single net driver.
An additional problem associated with the application of signals to semiconductor devices in such packages is the presence of net switching delays resulting in degraded system performance. Increases in performance by higher density technologies may be overwhelmed by increases in net loading.
A common practice in situations where several integrated devices, such as memory modules, are required to be responsive to common input signals is to provide discrete logic signal driver modules in addition to functional logic or memory modules required by the application. For example, in a particular application, a computer system might be designed to have a memory capacity of 1 Megabyte of storage. This would typically be implemented by providing a memory card including nine (9) 1Mbit dynamic random access memory (DRAM) modules. Since the initial memory and the remainder of the system were designed simultaneously, digital signal drivers are performance matched to the DRAMs provided. That is, the circuits designed by the, separately packaged, control processors are custom designed to provide logic signals, select and address signals, for 1M DRAM devices.
A subsequent enhanced product might offer a 4M Byte DRAM card which poses a problem in that the logic signals provided are incapable of driving the denser card. This problem has been solved by the provision of a DRAM module package containing one or more logic signal driver modules to redrive those signals intended to be coupled to the new 4M Byte card.
The application of such independent signal driver modules is described in the representative prior art such as the article "Extended Data Bus with Direction and Enable Control Features," by H. C. Lin et al, IBM Technical Disclosure Bulletin, Vol. 26, No. 10A, March 1984, pp. 5147-5152 or in U.S. Pat. No. 4,598,410 to Smith et al or in U.S. Pat. No. 4,698,826 to Denhez et al.
Because of the adaptation of the system to accommodate increased memory capacity, usually in the form of a circuit module or card designed to fit a physically constrained area, a problem is presented in how to physically place the increased capacity memory modules plus and one or more redriver modules in the space designed for memory modules alone. In addition, the requirement for separate redriver modules increases the cost of adding additional memory capacity by the cost of the redriver modules in addition to any increase due to the new memory modules and their associated packaging.
This invention enables the addition of modules having similar function, particularly in the case of memory modules, to a system without concern for physical space constraints or additional cost.